Patch ppc-support for FPM related Bug #51772

Patch version 2010-06-08 09:45 UTC

• 2010-06-08 09:45 UTC [diff to current]

Developer: tony2001@php.net

Index: sapi/fpm/fpm/fpm_atomic.h
===================================================================
--- sapi/fpm/fpm/fpm_atomic.h	(revision 300267)
+++ sapi/fpm/fpm/fpm_atomic.h	(working copy)
@@ -119,12 +119,130 @@
 /* }}} */
 #endif
 
+#elif ( __powerpc__ || __POWERPC__ )
+
+#if (SIZEOF_VOID_P == 8)
+
+typedef int64_t                     atomic_int_t;
+typedef uint64_t                   atomic_uint_t;
+typedef volatile          atomic_uint_t atomic_t;
+
+static inline atomic_uint_t atomic_cmp_set(atomic_t *lock, atomic_uint_t old, atomic_uint_t set) /* {{{ */
+{
+    atomic_uint_t  res, temp;
+
+    __asm__ volatile (
+
+    "    li      %0, 0       \n" /* preset "0" to "res"                      */
+    "    lwsync              \n" /* write barrier                            */
+    "1:                      \n"
+    "    ldarx   %1, 0, %2   \n" /* load from [lock] into "temp"             */
+                                 /*   and store reservation                  */
+    "    cmpd    %1, %3      \n" /* compare "temp" and "old"                 */
+    "    bne-    2f          \n" /* not equal                                */
+    "    stdcx.  %4, 0, %2   \n" /* store "set" into [lock] if reservation   */
+                                 /*   is not cleared                         */
+    "    bne-    1b          \n" /* the reservation was cleared              */
+    "    isync               \n" /* read barrier                             */
+    "    li      %0, 1       \n" /* set "1" to "res"                         */
+    "2:                      \n"
+
+    : "=&b" (res), "=&b" (temp)
+    : "b" (lock), "b" (old), "b" (set)
+    : "cc", "memory");
+
+    return res;
+}
+/* }}} */
+
+static inline atomic_int_t atomic_fetch_add(atomic_t *value, atomic_int_t add) /* {{{ */
+{
+    atomic_uint_t  res, temp;
+
+    __asm__ volatile (
+
+    "    lwsync              \n" /* write barrier                            */
+    "1:  ldarx   %0, 0, %2   \n" /* load from [value] into "res"             */
+                                 /*   and store reservation                  */
+    "    add     %1, %0, %3  \n" /* "res" + "add" store in "temp"            */
+    "    stdcx.  %1, 0, %2   \n" /* store "temp" into [value] if reservation */
+                                 /*   is not cleared                         */
+    "    bne-    1b          \n" /* try again if reservation was cleared     */
+    "    isync               \n" /* read barrier                             */
+
+    : "=&b" (res), "=&b" (temp)
+    : "b" (value), "b" (add)
+    : "cc", "memory");
+
+    return res;
+}
+/* }}} */
+
 #else
 
-#error unsupported processor. please write a patch and send it to me
+typedef int32_t                     atomic_int_t;
+typedef uint32_t                   atomic_uint_t;
+typedef volatile          atomic_uint_t atomic_t;
 
+static inline atomic_uint_t atomic_cmp_set(atomic_t *lock, atomic_uint_t old, atomic_uint_t set) /* {{{ */
+{
+    atomic_uint_t  res, temp;
+
+    __asm__ volatile (
+
+    "    li      %0, 0       \n" /* preset "0" to "res"                      */
+    "    eieio               \n" /* write barrier                            */
+    "1:                      \n"
+    "    lwarx   %1, 0, %2   \n" /* load from [lock] into "temp"             */
+                                 /*   and store reservation                  */
+    "    cmpw    %1, %3      \n" /* compare "temp" and "old"                 */
+    "    bne-    2f          \n" /* not equal                                */
+    "    stwcx.  %4, 0, %2   \n" /* store "set" into [lock] if reservation   */
+                                 /*   is not cleared                         */
+    "    bne-    1b          \n" /* the reservation was cleared              */
+    "    isync               \n" /* read barrier                             */
+    "    li      %0, 1       \n" /* set "1" to "res"                         */
+    "2:                      \n"
+
+    : "=&b" (res), "=&b" (temp)
+    : "b" (lock), "b" (old), "b" (set)
+    : "cc", "memory");
+
+    return res;
+}
+/* }}} */
+
+static inline atomic_int_t atomic_fetch_add(atomic_t *value, atomic_int_t add) /* {{{ */
+{
+    atomic_uint_t  res, temp;
+
+    __asm__ volatile (
+
+    "    eieio               \n" /* write barrier                            */
+    "1:  lwarx   %0, 0, %2   \n" /* load from [value] into "res"             */
+                                 /*   and store reservation                  */
+    "    add     %1, %0, %3  \n" /* "res" + "add" store in "temp"            */
+    "    stwcx.  %1, 0, %2   \n" /* store "temp" into [value] if reservation */
+                                 /*   is not cleared                         */
+    "    bne-    1b          \n" /* try again if reservation was cleared     */
+    "    isync               \n" /* read barrier                             */
+
+    : "=&b" (res), "=&b" (temp)
+    : "b" (value), "b" (add)
+    : "cc", "memory");
+
+    return res;
+}
+/* }}} */
+
 #endif
 
+#else
+
+#error unsupported processor. please write a patch and attach it to the report @ bugs.php.net
+
+#endif
+
 static inline int fpm_spinlock(atomic_t *lock, int try_once) /* {{{ */
 {
 	if (try_once) {
Index: sapi/fpm/config.m4
===================================================================
--- sapi/fpm/config.m4	(revision 300267)
+++ sapi/fpm/config.m4	(working copy)
@@ -505,6 +505,8 @@
 if test "$PHP_FPM" != "no"; then
   AC_MSG_RESULT($PHP_FPM)
 
+  AC_CHECK_SIZEOF(void *, 8)
+
   AC_LIB_EVENT([$minimum_libevent_version])
 
   PHP_ADD_LIBRARY_WITH_PATH(event, $LIBEVENT_PATH)